`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/11/07 21:08:17
// Design Name: 
// Module Name: Add_1bit_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module Add_1bit_tb(

    );
    
    reg A_tb, B_tb, CI_tb;
    wire Y_tb, CO_tb; 
    
    initial
    begin
        A_tb = 0; B_tb = 0; CI_tb = 0;
        #1000 A_tb = 0; B_tb = 0; CI_tb = 1;
        #1000 A_tb = 0; B_tb = 1; CI_tb = 0;
        #1000 A_tb = 0; B_tb = 1; CI_tb = 1;
        #1000 A_tb = 1; B_tb = 0; CI_tb = 0;
        #1000 A_tb = 1; B_tb = 0; CI_tb = 10;
        #1000 A_tb = 1; B_tb = 1; CI_tb = 0;
        #1000 A_tb = 1; B_tb = 1; CI_tb = 1;
    end
    
    Add_1bit_TOP add_1bit_TOP(
        .AA(A_tb),
        .BB(B_tb),
        .CCI(CI_tb),
        .YY(Y_tb),
        .CCO(CO_tb)
    );
endmodule
